TMS320C14, TMS320C15, TMS320C16FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS146N − FEBRUARY 2001 − REVISED MAY 2005power-down mode logic
Figure 9 shows the power-down mode logic on the C14/C15/C16.
CLKOUT4CLKOUT6Internal Clock TreeClockDistributionand DividersPD1PD2IFRIERPWRDCSRCPUPD3TMS320C14/15/16CLKIN
†
ClockPLLPower-DownLogicInternalPeripheralsRESETExternal input clocks, with the exception of CLKIN, are not gated by the power-down mode logic.
Figure 9. Power-Down Mode Logic†
triggering, wake-up, and effects
The power-down modes and their wake-up methods are programmed by setting the PWRD field (bits 15−10)of the control status register (CSR). The PWRD field of the CSR is shown in Figure 10 and described in Table 32.When writing to the CSR, all bits of the PWRD field should be set at the same time. Logic 0 should be used whenwriting to the reserved bit (bit 15) of the PWRD field. The CSR is discussed in detail in the TMS320C6000 CPUand Instruction Set Reference Guide (literature number SPRU1).
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TMS320C14, TMS320C15, TMS320C16FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS146N − FEBRUARY 2001 − REVISED MAY 2005Table 32. Characteristics of the Power-Down Modes
PRWD FIELD(BITS 15−10)000000001001010001
POWER-DOWN
MODENo power-down
PD1PD1
WAKE-UP METHOD
—
Wake by an enabled interruptWake by an enabled ornon-enabled interrupt
EFFECT ON CHIP’S OPERATION
—
CPU halted (except for the interrupt logic)
Power-down mode blocks the internal clock inputs at thePowerdown mode blocks the internal clock inputs at theboundary of the CPU, preventing most of the CPU’s logic fromswitching. During PD1, EDMA transactions can proceedbetween peripherals and internal memory.
Output clock from PLL is halted, stopping the internal clockstructure from switching and resulting in the entire chip beinghalted. All register and internal RAM contents are preserved. Allfunctional I/O “freeze” in the last state when the PLL clock isturned off.
Input clock to the PLL stops generating clocks. All register andinternal RAM contents are preserved. All functional I/O “freeze” inthe last state when the PLL clock is turned off. Following reset, thePLL needs time to re-lock, just as it does following power-up. Wake-up from PD3 takes longer than wake-up from PD2 becausethe PLL needs to be re-locked, just as it does following power-up.
—
011010PD2†Wake by a device reset
011100PD3†Wake by a device reset
All others
†
Reserved—
When entering PD2 and PD3, all functional I/O remains in the previous state. However, for peripherals which are asynchronous in nature orperipherals with an external clock source, output signals may transition in response to stimulus on the inputs. Under these conditions,peripherals will not operate according to specifications.
Cx power-down mode with an emulator
If user power-down modes are programmed, and an emulator is attached, the modes will be masked to allowthe emulator access to the system. This condition prevails until the emulator is reset or the cable is removedfrom the header. If power measurements are to be performed when in a power-down mode, the emulator cableshould be removed.
When the DSP is in power-down mode PD2 or PD3, emulation logic will force any emulation executioncommand (such as Step or Run) to spin in IDLE. For this reason, PC writes (such as loading code) will fail. A DSPreset will be required to get the DSP out of PD2/PD3.
power-supply sequencing
TI DSPs do not require specific power sequencing between the core supply and the I/O supply. However,systems should be designed to ensure that neither supply is powered up for extended periods of time(>1 second) if the other supply is below the proper operating voltage.power-supply design considerations
A dual-power supply with simultaneous sequencing can be used to eliminate the delay between core and I/Opower up. A Schottky diode can also be used to tie the core rail to the I/O rail (see Figure 11).